|The days of week is an example analog parameter TRUE FALSE.
The digital synchronous signal is discrete in both of time and value. TRUE FALSE.
Digital systems can operate with extreme reliability by using error‐correcting codes TRUE FALSE.
The minimum number of bits required to code four distinct elements is four TRUE FALSE.
In general, coding requires more bits than conversion TRUE FALSE.
The coding of a decimal number between 0 and 9 in BCD needs the same number of bits as the
conversion of this decimal number to its equivalent binary value TRUE FALSE.
Excess-3 is weighted coding method of decimal numbers where each digit in the decimal
number is coded into four bits TRUE FALSE.
Self-complementing property means that the 9's complement of a decimal number is obtained
directly by changing 1’s to 0's and 0's to 1's in its binary code TRUE FALSE.
6311 coding method uses only 10 combinations out of 16 to represent 10 decimal digits (0-9) TRUE FALSE.
The 7-bit ASCII binary codes takes the decimal range from 0 to 128 TRUE FALSE.
Parity bit method can detect and correct all single-bit errors TRUE FALSE.
Only the odd parity can detect an odd number of bit errors while the even parity cannot TRUE FALSE.
Unique truth table but different Boolean equations and logic diagrams can express a function TRUE FALSE.
In actual physical gates, if an input changes then the output change occurs instantaneously TRUE FALSE.
Switching algebra is a multi-valued form of Boolean algebra TRUE FALSE.
The dual of an algebraic expression is obtained by only interchanging + and . symbols TRUE FALSE.
An algebraic expression is self-dual when its dual is equal to the algebraic expression itself TRUE FALSE.
The absorption theorem states that:
(1) X + X’Y = X + Y
(2) X . (X’ + Y) = X . Y TRUE FALSE.
The De Morgan of an algebraic expression is obtained by taking the dual of the algebraic
expression and complementing each literal in it TRUE FALSE.
The De Morgan theorem of switching algebra is proved to be generalized to multiple number
of Boolean variables TRUE FALSE.
Minterm is AND term so it is also called the standard sum TRUE FALSE.
Standard product or standard sum are used to express Boolean function in standard form TRUE FALSE.
Boolean function of n variables has 2n/2 minterms and 2n/2 maxterms in its truth table TRUE FALSE.
(b + a + c) is a valid maxterm of a Boolean function TRUE FALSE.
ab is a valid minterm of a Boolean function TRUE FALSE.
Minterm evaluates to ‘1’ for its corresponding entry in the Boolean function truth table TRUE FALSE.
POM is an abbreviation of “Product of Minterms” canonical form TRUE FALSE.
Maxterm is the complement of minterm but not vice-versa TRUE FALSE.
The algebraic Boolean function expression: F = Y’ + X’Z’ can be written in SOM canonical form:
F = ∑(0, 1, 2, 4, 5) TRUE FALSE.
The algebraic Boolean function expression: G = A + B’C can be written in POM canonical form:
G = ∏(0, 2, 3) TRUE FALSE.
Given: F’(x, y, z) = ∏ (1, 3, 5, 7), then F(x, y, z) = ∑ (0, 2, 4, 6) TRUE FALSE.
Given: F’(x, y, z) = ∏ (1, 3, 5, 7), then F(x, y, z) = ∑ (1, 3, 5, 7) TRUE FALSE.
SOM of n-variable Boolean function is implemented as network of n-input AND gates
connected to an OR gate TRUE FALSE.
In general, canonical form must have fewer literals than standard form for Boolean function TRUE FALSE.
In general, canonical form must have more literals than standard form for Boolean function TRUE FALSE.
SOP and POS are simplified forms of SOM and POM respectively TRUE FALSE.
Each of AND, OR, XOR and XNOR gates can be extended to have more than two inputs TRUE FALSE.
A gate implements a positive logic AND function will implement a negative logic OR function,
and vice-versa TRUE FALSE.
Circuit optimization is a more formal approach to simplification that requires three cost
criteria to measure the simplicity of a circuit TRUE FALSE.
Each square in K-map represents a maxterm TRUE FALSE.
Each square in K-map represents a minterm TRUE FALSE.
On 3-variable K-map, a combined eight adjacent squares represent 0-variable term TRUE FALSE.
AND-Invert and Invert-OR both represent NAND gate TRUE FALSE.
A 2-level POS circuit can be converted easily to a NAND-NAND implementation TRUE FALSE.
A 2-level POS circuit can be converted easily to a SOP implementation TRUE FALSE.
NAND and NOR gates are neither commutative nor associative TRUE FALSE.
NAND and NOR gates are commutative & associative TRUE FALSE.
A NOR gate with one input is an inverter TRUE FALSE.
NOR-NOR implementation requires function to be in POM/POS form TRUE FALSE.
To implement a Boolean function as two-level NOR-OR circuit, its 0’s in the k-map must be
combined into SOP form TRUE FALSE.
XOR and XNOR are also known as the odd and even functions respectively TRUE FALSE.
XOR and XNOR functions are associative but not commutative TRUE FALSE.
Analysis finds out function of given circuit, while design determines circuit of given function TRUE FALSE.
The full adder circuit can be implemented using two cascaded half adder circuits TRUE FALSE.
When two signed binary numbers are added, an overflow can be detected from the end carry
out of the most significant bit position TRUE FALSE.
The digital asynchronous signal is ......... in time and ......... in value discrete - continuous discrete - discrete continuous – discrete continuous – continuous.
The electrical signals in most present‐day digital systems use just ......... discrete values 2 3 4 5.
The number of bits, n, is required to code at maximum distinct elements n^3 n * log(n) 2^n n^2.
A number with n decimal digits is coded with .......... bits in Excess-3 2n 4n n^3 n^2.
he weights of BCD code
are ......... 8,4,2,1 6,3,1,1 6,4,2,1 84-2-1.
All the following binary coding methods are self-complementing except ......... BCD Excess-3 2421 84-2-1.
2421 binary coding methods codes each decimal digit into . bits 9 6 4 2.
The Excess-3 code of the decimal number, (945)10, is .......... 110001111000 1001100101 1110110001 100101000101.
Error correction during transmission of .........-coded decimal digits is easiest of all other
binarycodes because only 1 bit changes from one binary value to the next value BCD Gray Excess3 ASCII.
The extended-ASCII uses .........-bit to code 128 elements of the alphanumeric character set 32 7 8 16.
There are .......... basic binary logical operations. 2 3 4 5.
The decoded decimal value of (100010010111)2 in 84-2-1 coding is ........ (564)10 (871)10 (897)10 (675)10.
An 8-bit binary code is decoded into ......... -digit decimal number using 6432 coding 4 2 3 6.
The theorem of Boolean algebra states that: (1) X + X = X (2) X . X = X is named involution complement idempotence identity.
The postulate of Boolean algebra states that: (1) X + Y = Y + X (2) X . Y = Y . X is named ....... associative distributive commutative De Morgan.
The precedence of Boolean operators from the highest to the lowest written in order
from the left to the right is .......... NOT, AND, OR, Parentheses Parentheses, AND, NOT, OR NOT, Parentheses, AND,OR Parentheses, NOT, AND,OR.
The ......... theorem states that: AB + A’C + BC = AB + A’C simplification consensus minimization absorption.
is AND term with every variable present in either true or complemented form Product Maxterm Minterm Sum.
Standard sum is another name of ...... product maxterm sum minterm.
For ........., ‘1’ in its binary index means that the corresponding variable is normal (not
complemented) while ‘0’ means that the corresponding variable is complemented. product minterm maxterm sum.
is a canonical form that expresses Boolean function by “ANDing” its standard sums
corresponding to ‘0’ entries in the Boolean function truth table POM POS SOM SOP.
The equivalent algebraic expression of the canonical form: F(a, b, c, d) = ∏(1, 3, 6, 11) is ... ( b + c + d’ ) . ( b + c’ + d’ ) . ( b’ + c’ + d ) . ( a’ + b + c’ + d’ ) ( a’ + b’ + c’ + d ) . ( a’ + b’ + c + d ) . ( a’ + b + c + d’ ) . ( a + b’ + c + d ) ( a + b + c + d’ ) . ( a + b + c’ + d’ ) . ( a + b’ + c’ + d ) . ( a’ + b + c’ + d’ ) ( c + d’ ) . ( c’ + d’ ) . ( b’ + c’ + d ) . ( a’ + b + c’ + d’ ).
The canonical form: ..........is the equivalent to the following algebraic expression:
a’b’c’d’ + a’b’c’d + abc’d’ + abcd G(a, b, c, d) = ∑(0, 1, 12, 15 G(a, b, c, d) = ∏(0, 1, 12, 15) G(a, b, c, d) = ∏(0, 3, 14, 15) G(a, b, c, d) = ∑(0, 3, 14, 15).
The form of POM or POS is implemented as network from two-levels of .......... gates ORs-AND ANDs-AND ORs-OR ANDs-OR.
The algebraic expression F(A, B, C) = (B + C).(A + C) is in .......... form SOP POS POM SOM.
A gate can be extended to multiple inputs if the binary operation it represents is .... commutative and distributive commutative and associative associative and distributive associative and De Morgan.
binary Boolean operations are commutative but not associative, so they are not
extendable to more than two inputs AND and OR NAND and NOR Buffer and Inverter XOR and XNOR.
are known as the odd and even functions respectively XOR and XNOR AND and OR Buffer and Inverter NAND and NOR.
A gate implements a positive logic OR function will implement a negative logic ......... function. NOR AND XNOR XOR.
F = ( A + C’ ) . ( B’ + C ) . ( A’ + B ) has the following costs: ...... L = 6, G = 8 and GN = 11 L = 6, G = 9 and GN = 12 L = 3, G = 6 and GN = 9 L = 3, G = 9 and GN = 12.
By combining adjacent squares in K-map, we reduce number of literals in an output ... minterm maxterm product term sum term.
On 4-variable K-map, a combined four adjacent squares represent .........-variable term 0 2 3 4.
The optimum POS of F(W, X, Y, Z) = ∑ (1, 2, 3, 9, 10, 11, 13, 14, 15) is ..... F(W, X, Y, Z) = WZ + WY + X’Z + X’Y F(W, X, Y, Z) = Y’Z’ + W’X F(W, X, Y, Z) = ( Y’ + Z’) ( W’+ X ) F(W, X, Y, Z) = ( Y + Z ) ( W + X’ ).
The optimum SOP of F(A, B, C, D) = ∑ (3, 9, 11, 12, 13, 14, 15) + ∑d (1, 4, 6) is ..... F(A, B, C, D) = A’B + B’D’ F(A, B, C, D) = AB + B’D F(A, B, C, D) = (A + B’) . (B + D) F(A, B, C, D) = (A’ + B’) . (B + D’).
The optimum SOP of F(A, B, C, D) = ∑ (0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15) has .......... essential
prime implicants 0 1 2 3.
Invert-AND represents ......... gate. NAND NOR XOR XNOR.
AND is equivalent to ......... with inverted inputs XNOR XOR NOR NAND.
Two-level ......... circuit can be easily converted to NOR-NOR implementation AND-OR OR-AND-Invert AND-OR-Invert OR-AND.
AND-OR-Invert implementation of a circuit can be easily converted to .... NAND-AND OR-NAND NOR-OR AND-NAND.
is also known as the equivalence function. XNOR XOR NOR NAND.
gates are used for implementing parity generators and checkers circuits XOR and XNOR Buffer and inverted NAND and NOR AND and OR.
To check for errors in the even parity of 3-bit codes, it is needed to use ..........checker circuit. 3-bit odd function 4-bit odd function 3-bit even function 4-bit even function.
To perform circuit analysis, a ........ must be provided as an input to the analysis process. truth table logic diagram Boolean function problem statement.
The carry output of half adder circuit has the same truth table of ......... gate AND OR NOR NAND.
The full adder circuit adds ......... bits together. 2 3 4 5.
Overflow occurs if the two binary numbers added are ..... both positive or both negative both positive both negative one of them is positive and the other is negative.
Active-low decoder is implemented with .......... gate. OR AND NAND NOR.
selects binary information from one of many input lines and directs it to a single output
line multiplexer encoder decoder adder.